1. Field
Invention relates to electronic design automation (EDA), particularly to automated design process and method for semiconductor chip implemented with multi-rail cells, wherein multi-rail circuit and logic design employ multi-VDD, back bias, sleep transistors, retention grids, etc.
2. Related Art
In semiconductor chip design, tools commonly classified as electronic design automation (EDA) software are used to provide means for automating design of Integrated Circuits (IC) and Systems on Chip (SoC). Tools are also used to provide means of automating task(s) of preparing design for manufacture on silicon.
Moreover Hardware Description Languages (HDL) are used to model semiconductor chip and functions. Existing HDL technology places main function description of IC and SoC in Register Transfer Language (RTL) source files.
RTL files do not include information about various “non-functional” aspects of the design. One of such “non-functional” aspects is voltage island connection of multi-rail cells wherein multi-rail circuit and logic design employ multi-VDD, back bias, sleep rails, retention grids, etc. Such inability to represent such an architectural choice of voltage elements in RTL inhibits development of design automation methods. Hence, it is not possible to simulate, synthesize, perform physical design or formally verify semiconductor chip design implemented with multi-rail cells without hardship and risk of failure. Voltages are often key functionality factors; and treating them as “non-functional” is thus problematic. Accordingly, there is need for improved design process and method.